中英
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sequential circuit中文是什么意思
- 中文翻譯
- 造句
- 【電學(xué)】程序電路。
- sequential adj. 1.繼續(xù)的；連續(xù)的；隨著…而發(fā)生的 (to)。 ...
- circuit n. 1.(某一范圍的)周邊一圈；巡回，周游；巡回路線[ ...
- asynchronous sequential circuit 異步時序電路
- autonomous sequential circuit 自激時序電路
- clocked sequential circuit 時鐘進(jìn)序電路; 時鐘時序電路
- complex sequential circuit 復(fù)式時序電路
- flip-flop sequential circuit 觸發(fā)器時序電路
- iterative sequential circuit 累接時序電路
- linear sequential circuit 線性時序電路
- pulse mode sequential circuit 脈沖式進(jìn)序電路
- sequential flasher circuit 順序閃光回路
- sequential logic circuit 時序邏輯電路
- sequential logical circuit 時序邏輯電路
- sequential start circuit 程序起動電路
- sequential switch circuit 時序開關(guān)電路
- sequential switching circuit 依次轉(zhuǎn)換電路; 依次轉(zhuǎn)接電路
- synchronous sequential circuit 同步時序電路
- sequential adj. 1.繼續(xù)的；連續(xù)的；隨著…而發(fā)生的 (to)。 2.結(jié)果的。 3.〔美俚〕(避孕丸)按期服食的。 n. 〔pl.〕 〔美俚〕按期服食的避孕丸。 adv. -ly
- access sequential 序列存取
- bit sequential 位序列的
- chain, sequential 序列鏈路
- construct, sequential 序列構(gòu)造
- control, sequential 順序控制
- dot sequential 點(diǎn)順序制的
- dot-sequential adj. 【無線電】(彩色電視)點(diǎn)順序制的。
- Verification of sequential circuit design based on obdd
時序電路設(shè)計(jì)的驗(yàn)證 - Asynchronous transmission sequential circuit
傳送信號減衰 - Asynchronous sequential circuit
異步時序電路 - Autonomous sequential circuit
自激時序電路 - We also develop a new word - level fault parallel fs algorithin for synchronous sequential circuits
接著又開發(fā)了一個新的單機(jī)字級故障并行fs算法。 - The content of this thesis just is parallel atpg algorithlms and it prototype system for non - scan synchionous sequential circuits
本文的研究內(nèi)容正是面向非掃描同步時序電路的并行atpg算法。 - Most of vlsi circuits are sequential circuits . sequential circuits can be simulated by symbolic finite state machine ( fsm )
Vlsi系統(tǒng)中大部分是時序電路，時序電路可以用符號化的有限狀態(tài)機(jī)( finite - state - machine ，簡稱fsm )來模擬。 - Although some scholars have done lots of work on the test generation of the digital circuits , it is still a well - known puzzle to test sequential circuits
雖然各國學(xué)者在數(shù)字電路測試生成上已做了大量的工作，時序電路的測試生成仍然是公認(rèn)的難題。 - The sy - stem had different requirements on time sequence in high - speed clock and low - speed clock situations , which resulted in the complexity of the sequential circuit
在高速時鐘和低速時鐘的情況下，系統(tǒng)有不同的時序要求，這就決定了時序電路的復(fù)雜性。 - The international standard sequential circuits iscas ' 89 ( addendum ' 93 included ) is used to verify the algorithm , and the results are better than other algorithms "
采用國際標(biāo)準(zhǔn)時序電路iscas ’ 89 (包括addendum ’ 93 )進(jìn)行了算法驗(yàn)證，取得了優(yōu)于文獻(xiàn)中其它算法的結(jié)果。
- sequential circuitとは意味：シーケンス回路｛かいろ｝
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